Paper Title :Design & Simulation Of 32-Bit Floating Point ALU
Author :Kavita Katole, Ashwin Shinde, Sumedha Chokhandre, Bhushan Manjre, Nirja Dharmale
Article Citation :Kavita Katole ,Ashwin Shinde ,Sumedha Chokhandre ,Bhushan Manjre ,Nirja Dharmale ,
(2014 ) " Design & Simulation Of 32-Bit Floating Point ALU " ,
International Journal of Advances in Science, Engineering and Technology(IJASEAT) ,
pp. 72-74,
Volume-2,Issue-2
Abstract : Abstract— VHDL environment for floating point arithmetic and logic unit design is introduced the novelty in the ALU design
which provides a high performance ALU to execute multiple instructions simultaneously. In top-down design approach,
arithmetic modules, addition, subtraction, multiplication, division, comparison & logical functions are combined to form a
floating point ALU unit. Each module is divided into sub- modules with four selection bits are combined to select a particular
operation. Each module is independent to each other. The modules are realized and validated using VHDL simulation in the
Active HDL software.
Type : Research paper
Published : Volume-2,Issue-2
DOIONLINE NO - IJASEAT-IRAJ-DOIONLINE-628
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Copyright: © Institute of Research and Journals
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Published on 2014-04-16 |
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