International Journal of Advances in Science, Engineering and Technology(IJASEAT)
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Volume-8,Issue-2  ( Apr, 2020 )
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Submitted Papers : 80
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  Journal Paper

Paper Title
Design & Simulation Of 32-Bit Floating Point ALU

Abstract— VHDL environment for floating point arithmetic and logic unit design is introduced the novelty in the ALU design which provides a high performance ALU to execute multiple instructions simultaneously. In top-down design approach, arithmetic modules, addition, subtraction, multiplication, division, comparison & logical functions are combined to form a floating point ALU unit. Each module is divided into sub- modules with four selection bits are combined to select a particular operation. Each module is independent to each other. The modules are realized and validated using VHDL simulation in the Active HDL software.

Author - Kavita Katole, Ashwin Shinde, Sumedha Chokhandre, Bhushan Manjre, Nirja Dharmale

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| Published on 2014-04-16
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