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Paper Title :
The New Era On Low Power Design And Verification Methodology

Author :Naveen Kumar Challa, Usha Rani Nelakuditi

Article Citation :Naveen Kumar Challa ,Usha Rani Nelakuditi , (2016 ) " The New Era On Low Power Design And Verification Methodology " , International Journal of Advances in Science, Engineering and Technology(IJASEAT) , pp. 160-165, Volume-4,Issue-3

Abstract : In earlier days, after IC is fabricated the main objective is to verify the functionality. Since overlook of errors at this level causes big loss in terms of money and time, if errors occurs during design/coding level according to the law of ten. .But current day paradigm has been shifted to power instead of functionality due to demand of high speed VLSI structures together with network processors in networking or SOCs in communication. Keep this in view this paper deals with the review of various power aware designs like clock gating, power gating, dynamic voltage scaling and frequency scaling. It also explains recent popular IEEE 1801Unified power format (UPF) used for design and verification of low power Integrated Circuits.UPF translated energy design into an executable hierarchical parallel system design. This method is a systematic approach and paves the solution to many critical designs. Index Terms— Low Power Verification, Unified Power Format, Register Transfer Level, Power-Aware design, Clock gating, Power gating, Frequency scaling.

Type : Research paper

Published : Volume-4,Issue-3


DOIONLINE NO - IJASEAT-IRAJ-DOIONLINE-5203   View Here

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