International Journal of Advances in Science, Engineering and Technology(IJASEAT)
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Volume-7,Issue-3  ( Jul, 2019 )
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Submitted Papers : 80
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  Journal Paper

Paper Title
A Low Leakage Nanoscale CMOS Memory Cell With Virtual Grounding

Abstract
In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power,leakage & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area, leakage & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results


Author - L.Krishnaveni, T.Venkatasridhar

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| Published on 2014-01-22
   
   
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