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Paper Title :
A Low Leakage Nanoscale CMOS Memory Cell With Virtual Grounding

Author :L.Krishnaveni, T.Venkatasridhar

Article Citation :L.Krishnaveni ,T.Venkatasridhar , (2013 ) " A Low Leakage Nanoscale CMOS Memory Cell With Virtual Grounding " , International Journal of Advances in Science, Engineering and Technology(IJASEAT) , pp. 51-54, Volume-1,Issue-2

Abstract : In this paper we are going to modify the Schmitt Trigger based SRAM for the purpose of more reduced power,leakage & area than the existing type of designs as well as the new design which is combined of virtual grounding with read Error Reduction Logic is compared with the existing technologies & the nanometer technology is also improved for the purpose of much improved reduction of area, leakage & power factors than the Schmitt Trigger based SRAM Designs the simulations were done using microwind & DSCH results

Type : Research paper

Published : Volume-1,Issue-2


DOIONLINE NO - IJASEAT-IRAJ-DOIONLINE-310   View Here

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