Paper Title
Pdn Optimization Of 3dic’s Using Tsv Technology

Through Silicon-via [TSV] and die-stacking are the two important technologies available for three-dimensional Integrated Circuits [3D IC’s]. This TSV technology brings the performance improvement through the reduction of wire length and footprint area. But compared to 2-D IC’s, the 3-D IC’s have several challenges for power delivery network design due to larger supply currents and longer power delivery paths. In 3-D IC, the power delivery network with flip chip package is mainly compared of Power/Ground [P/G] bumps and P/G TSV’s. It is very important to optimize their P/G bumps and P/G TSV’s together by satisfying the IR-drop constraints because the number of P/G bumps is limited and the size of P/G TSV is larger than that of standard cell. In this paper, we obtained an effect of the number of power bumps and power TSV’s on the IR-drop in 3-D IC floor plan level and proposed the methodology, which will optimizes the number and position of both power bumps and power TSV’s at a time.