Design Of Low Power Asynchronous 6 Transistor Sram In 45nm Cmos With The Use Of Pass Transistor Based Tree Decoders And Static Cmos Based Timing Circuitry Along With Process Variation Simulation
This paper describes the design of a 6 Transistor Static Random Access Memory (6T SRAM) in 45nM CMOS
along with the design of the peripheral components such as the pass transistor based tree decoders and static CMOS based
tim ing circuit. The basic memory-cell is simulated for read and write- margin variations with a 10% variation in threshold
voltage and the complete system design is simulated using test patterns of repetitive 1s and0s. At a clock frequency of
250MHz, the design consumes 28.6fJ/bit.