Paper Title
Reduced Area Fully Parallel And Fully Serial Fir Filter On Field-Programmable Gate Array
Abstract
In this paper fully serial and fully parallel FIR filters are designed with different quantization on FPGA for low
area requirement. Modified fully serial and fully parallel band-pass FIR filters with same specification as in reference paper
designed and simulated on ISE. The suggested implementations are synthesized with Xilinx ISE 14.2 version. Results show
that compare with reference paper low area and better speed are achieved